View BR34E02FVT-W_4941482.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Memory for Plug & Play
DDR/DDR2 (For memory module) SPD Memory
BR34E02FVT-W, BR34E02NUX-W
Description BR34E02FVT-W is 256x8 bit Electrically Erasable PROM (Based on Serial Presence Detect) Features 1) 256x8 bit architecture serial EEPROM 2) Wide operating voltage range: 1.7V-3.6V 3) Two-wire serial interface 4) High reliability connection using Au pads and Au wires 5) Self-Timed Erase and Write Cycle 6) Page Write Function (16byte) 7) Write Protect Mode Settable Reversible Write Protect Function: 00h-7Fh Write Protect 1 (Onetime Rom) : 00h-7Fh Write Protect 2 (Hardwire WP PIN) : 00h-FFh 8) Low Power consumption Write (at 1.7V ) : 0.4mA (typ.) Read (at 1.7V ) : 0.1mA(typ.) Standby ( at 1.7V ) : 0.1A(typ.) 9) DATA security Write protect feature (WP pin) Inhibit to WRITE at low VCC 10) Compact package: TSSOP-B8, VSON008X2030 11) High reliability fine pattern CMOS technology 12) Rewriting possible up to 1,000,000 times 13) Data retention: 40 years 14) Noise reduction Filtered inputs in SCL / SDA 15) Initial data FFh at all addresses BR34E02-W Series Capacity 2Kbit
No.09002EAT03
Bit format 256X8
Type BR34E02-W
Power Source Voltage 1.7V3.6V
TSSOP-B8
VSON008X2030
Absolute Maximum Ratings (Ta=25) Parameter Supply Voltage Power Dissipation Storage Temperature Operating Temperature Terminal Voltage (A0) Terminal Voltage (etcetera)
* Reduce by 3.3mW(*1), 3.0 mW(*2)/C over 25C
Symbol VCC Pd Tstg Topr -
Rating -0.3+6.5 330(BR34E02FVT-W) 300(BR34E02NUX-W) -65+125 -40+85 -0.310.0 -0.3VCC+0.3
*1 *2
Unit V mW V V
Recommended operating conditions Parameter Supply Voltage Input Voltage
Symbol VCC IN
Rating 1.73.6 0VCC
Unit V V
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
1/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Memory cell characteristics(Ta=25, VCC=1.7V3.6V) Specification Parameter Min. Typ. Write / Erase Cycle *1 1,000,000 *1 Data Retention 40 *1:Not 100% TESTED
Technical Note
Max. -
Unit Cycles Years
Electrical characteristics - DC(Unless otherwise specified Ta=-40+85, VCC=1.7V3.6V) Specification Parameter Symbol Unit Test Condition Min. Typ. Max. "H" Input Voltage VIH1 0.7 VCC Vcc+0.3 V "L" Input Voltage VIL1 0.3 VCC V "L" Output Voltage 1 VOL1 -0.3 0.4 V IOL=2.1mA2.5VVCC3.6V(SDA) "L" Output Voltage 2 VOL2 0.2 V IOL=0.7mA1.7VVCC2.5V(SDA) Input Leakage Current 1 ILI1 -1 1 A VIN=0VVCC(A0,A1,A2,SCL) Input Leakage Current 2 ILI2 -1 15 A VIN=0VVCC(WP) Input Leakage Current 3 ILI3 -1 20 A VIN=VHV(A0) Output Leakage Current ILO -1 1 A VOUT=0VVCC VCC=1.7V,fSCL=100kHztWR=5ms Byte Write ICC1 1.0 mA Page Write Write Protect VCC =3.6V,fSCL=100kHz, tWR=5ms Byte Write Operating Current ICC2 3.0 mA Page Write Write Protect VCC =3.6V,fSCL=100kHz Random Read ICC3 0.5 mA Current Read Sequential Read VCC =3.6V,SDA,SCL= VCC Standby Current ISB 2.0 A A0,A1,A2=GND,WP=GND A0 HV Voltage VHV 7 10 V VHV-Vcc4.8V
Note: This IC is not designed to be radiation-resistant.
lectrical characteristics - AC(Unless otherwise specified Ta=-40+85, VCC =1.7V3.6V) STANDARD-MODE FAST-MODE 1.7VVCC5.5V 2.5VVCC5.5V Parameter Symbol Min. Typ. Max. Min. Typ. Max. Clock Frequency fSCL 400 100 Data Clock High Period tHIGH 0.6 4.0 Data Clock Low Period tLOW 1.2 4.7 SDA and SCL Rise Time *1 tR 0.3 1.0 SDA and SCL Fall Time *1 tF 0.3 0.3 Start Condition Hold Time tHD:STA 0.6 4.0 Start Condition Setup Time tSU:STA 0.6 4.7 Input Data Hold Time tHD:DAT 0 0 Input Data Setup Time tSU:DAT 100 250 Output Data Delay Time tPD 0.1 0.9 0.1 3.5 Output Data Hold Time tDH 0.1 0.1 Stop Condition Setup Time tSU:STO 0.6 4.0 Bus Free Time tBUF 1.2 4.7 Write Cycle Time tWR 5 5 Noise Spike Width (SDA tI 0.1 0.1 and SCL) WP Hold Time tHDWP 0 0 WP Setup Time tSUWP 0.1 0.1 WP High Period tHIGHWP 1.0 1.0 *1Not 100 TESTED
Unit kHz s s s s s s ns ns s s s s ms s ns s s
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
2/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
Fast / Standard Modes Fast mode and Standard mode differ only in operation frequency. Operations performed at 100kHz are considered in "Standard-mode", while those conducted at 400kHz are in "Fast-mode". Please note that these clock frequencies are maximum values. At lower power supply voltage it is difficult to operate at high speeds. The EEPROM can operate at 400kHz, between 2.5V and 3.6V, and at 100kHz from 1.7V-2.5V. Synchronous Data Timing
tR SCL tHD:STA SDA (IN) tBUF SDA (OUT)
tF
tHIGH
SCL
tSU:DAT tLOW tHD:DAT
tSU:STA
SDA
tHD:STA
tSU:STO
tPD
tDH
START BIT
STOP BIT
Fig.1-(a) Synchronous Data Timing SDA data is latched into the chip at the rising edge of SCL clock. Output data toggles at the falling edge of SCL clock.
SCL
SCL
Fig.1-(b) Start/Stop Bit Timing
DATA(1) SDA D1 D0 ACK
DATA(n) ACK WR
SDA
D0
WRITE DATA(n)
ACK
tWR
STOP CONDITION START CONDITION
WP
Stop Condition
tSUWP
HDWP
Fig.1-(c) Write Cycle Timing
Fig.1-(d) WP Timing Of The Write Operation
SCL DATA(1) SDA D1 D0 ACK tHIGH:WP WP DATA(n) ACK tWR
Fig.1-(e) WP Timing Of The Write Cancel Operation For WRITE operation, WP must be "Low" from the rising edge of the clock (which takes in D0 of first byte) until the end of tWR. (See Fig.1-(d) ) During this period, WRITE operation can be canceled by setting WP "High".See Fig.1-(e) When WP is set to "High" during tWR, WRITE operation is immediately ceased, making the data unreliable. It must then be re-written.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
3/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Block diagram
Technical Note
A0 1
8bit
PROTECT_MEMORY_ARRY 2Kbit_MEM ORY_ARRY
8 VCC
8bit
A1 2
ADDRESS DECODER
8bit
SLAVE , WORD ADDRESS GS
STOP
DATA REGISTE
7 WP
START
A2 3
CONTOROL LOGIC
ACK
6 SCL
GND 4
HIGH VOLTAGE
VCC LEVEL
5 SDA
Fig.2 Blo Pinout diagram and description Pin Name A0 1 A1 2 A2 3 GND 4 Fig.3 Pin Configuration
BR34E02FVT-W BR34E02NUX-W
Input/Output IN IN IN / OUT IN Power Supply Ground 0V
Functions
8 VCC 7 WP 6 SCL
VCC GND A0,A1,A2 SCL SDA
Slave Address Set. Serial Clock Input Slave and Word Address, Serial Data Input, Serial Data Output Write Protect Input
*2 *1
5 SDA WP
*1 Open drain output requires a pull-up resistor. *2 WP Pin has a Pull-Down resistor. Please leave unconnected or connect to GND when not in use.
Electrical characteristics curves The following characteristic data are typ. value.
6 5 4 VIL1,2[V]
1
0.8
SPEC
3 2
Ta=85 Ta=-40 Ta=25
VOL1[V]
0.6
SPEC
0.4
Ta=85
0.2
Ta=85 Ta=-40 Ta=25
Ta=25
1 0 0 1 2 VCC[V] 3
SPEC
4
0 0 1 2 IOL1[mA] 3
Ta=-40
4
Fig.4 "H" Input Voltage VIH (A0,A1,A2,SCL,SDA,WP)
1
Fig.5 "L" Input Voltage VIL (A0,A1,A2,SCL,SDA,WP)
1.2
Fig.6 "L" Output Voltage VOL1-IOL1 (VCC=2.5V)
16
SPEC
0.8 1 12 0.8 ILI1[ A] VOL2[V] 0.6 0.6 0.4 4 0.2 ILI2[A] 8
SPEC
0.4
Ta=85 SPEC Ta=25
0.2
Ta=-40
0 0 1 2 IOL2[mA] 3 4 0 0 1 2 VCC[V]
Ta=85 Ta=25 Ta=-40
0 3 4 0 1
Ta=85 Ta=25 Ta=-40
2 VCC[V]
3
4
Fig.7 "L" Output Voltage VOL2-IOL2 (VCC=1.7V)
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
Fig.8 Input Leakage Current ILI1 (A0,A1,A2,SCL,SDA) 4/18
Fig.9 Input Leakage Current ILI2 (WP)
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
3.5
SPEC1
0.6 0.5
SCL=400kHz(VCC2.5V) fSCL=100kHz(1.7VVccV) DATA=AA SPEC
2.5
SPEC
3 2.5 ICC1,2[mA] 2 1.5 1 0.5 0 0 1 2 VCC[V] 3 4
Ta=25 Ta=85 Ta=-40
2
fSCL=100kHz DATA=AAh
0.4 ICC3[mA] 0.3 0.2 0.1
ISB[A]
Ta=85 Ta=25
1.5
SPEC2
1
0.5
Ta=40
Ta=85 Ta=25 Ta=-40
0 0 1 2 VCC[V] 3 4
0 0 1 2 VCC[V] 3 4
Fig.10 Write Operating Current ICC1,2 (fSCL=100kHz,400kHz)
Fig.11 Read Operating Current ICC3 (fSCL=400kHz)
Fig.12 Standby Current ISB
10000
Ta=85 Ta=25 Ta=-40
5
SPEC2
5
SPEC2
4
1000 fSCL[kHz] tHIGH[s] tLOW[s]
SPEC1
4
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
100
SPEC2
2
Ta=-40 Ta=25 Ta=85 SPEC1
2
SPEC1
10
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
1
Ta=85 Ta=25 Ta=-40
1
1 0 1 2 VCC[V] 3 4
0 0 1 2 VCC[V] 3 4
0 0 1 2 VCC[V] 3 4
Fig.13 Clock Frequency fSCL
Fig.14 Data Clock High Period tHigh
Fig.15 Data Clock Low Period tLow
5
SPEC2
5
50
SPEC2 SPEC1,2
4 tHD:STA[s]
4
0 tHD:DAT(HIGH)[s]
=85 Ta=25 Ta=-40
tSU:STA[s]
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=-40 Ta=25 Ta=85
3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
2
-50
2
1
SPEC1
1
Ta=-40 Ta=25 Ta=85 SPEC1
-100
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
-150
0 0 1 2 VCC[V] 3 4
0 0 1 2 VCC[V] 3 4
-200 0 1 2 VCC[V] 3 4
Fig.16 Start Condition Hold Time tHD:STA
Fig.17 Start Condition Setup Time tSU:STA
FiagmDag.18 ck DiTarata HoldimtHD:DAT(High)
50
300
SPEC2
300
SPEC2
0 tHD:DAT(LOW)[s]
SPEC1,2
200 tSU:DAT(HIGH)[ns]
tSU:DAT(LOW)[ns]
200
-50
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
SPEC1
100
-100
Ta=85
0
Ta=85 SPEC1 Ta=25 Ta=-40
100
Ta=85
0
Ta=25 Ta=-40 SPEC1:FAST-MODE SPEC2:STANDARD-MODE
-150
Ta=25 Ta=-40
-100
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
-100
-200 0 1 2 VCC[V] 3 4
-200 0 1 2 VCC[V] 3 4
-200 0 1 2 VCC[V] 3 4
Fig.19 Data Hold Time tHD:DAT(LOW)
Fig.20 Input Data Setup Time tSU:DAT(HIGH)
Fig.21 Input Data Setup Time tSU:DAT(LOW)
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
5/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
4
SPEC2
4
5
SPEC2
3
tDH[s]
3
tSU:STO[s]
4
tPD[s]
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
3
2
SPEC1 Ta=85 Ta=25 Ta=-40
2
SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=85 Ta=25 Ta=-40
2
1
1
SPEC2
SPEC2 SPEC1
Ta=85 Ta=25 Ta=-40
1
SPEC1
0 0
SPEC1
0 0
0
1
2 VCC[V]
3
4
0
1
2 VCC[V]
3
4
1
2 VCC[V]
3
4
Fig.22 Output Data Delay Time tPD
Fig.23 Output Data Hold Time tDH
Fig.24 Stop Condition Setup Time tSU:STO
5
SPEC2
6
SPEC1,2
0.6 0.5 0.4 0.3
SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=-40
4
5
Ta=-40
tI(SCL H)[s]
4 tBUF[s]
SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=85
tWR[ms]
3
Ta=25
Ta=25 Ta=85
3 2 1 0
2
Ta=85
0.2
SPEC1,2
1
SPEC1
Ta=25 Ta=-40
0.1
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
0 0 1 2 VCC[V] 3 4
0 4 0 1 2 VCC[V] 3 4
0
1
2 VCC[V]
3
Fig.25 Bus Free Time tBUF
Fig.26 Write Cycle Time tWR
Fig.27 Noise Spike Width tI(SCL H)
0.6 0.5 0.4 0.3 0.2 0.1 0 0 1 2 VCC[V] 3 4
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
0.6 0.5 tI(SDA H)[s] 0.4 0.3 0.2 0.1 0 0 1 2 VCC[V] 3 4
Ta=25 Ta=85 SPEC1:FAST-MODE SPEC2:STANDARD-MODE Ta=-40
0.6 0.5 0.4 0.3 0.2 0.1
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
tI(SDA L)[s]
tI(SCL L)[s]
Ta=25
Ta=-40
Ta=-40 Ta=25 Ta=85 SPEC1,2
Ta=85
SPEC1,2
SPEC1,2
0 0 1 2 VCC[V] 3 4
Fig.28 Noise Spike Width tI(SCL L)
Fig.29 Noise Spike Width tI(SDA H)
Fig.30 Noise Spike Width tI(SDA L)
0.2
SPEC1,2
1.2 1 tHIGH:WP[s] 0.8 0.6 0.4 0.2 0
0 1 2 VCC[V] 3 4
Ta=-40 Ta=25 Ta=85 SPEC1:FAST-MODE SPEC2:STANDARD-MODE SPEC1,2
0 tSU:WP[s]
SPEC1:FAST-MODE SPEC2:STANDARD-MODE
-0.2
Ta=85 Ta=25
-0.4
Ta=-40
-0.6
0
1
2 VCC[V]
3
4
Fig.31 WP Setup Time tSU:WP
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
Fig.32 WP High Period tHigh:WP 6/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
2 Data transfer on the I C BUS Data transfer on the I2C BUS The BUS is considered to be busy after the START condition and free a certain time after the STOP condition. Every SDA byte must be 8-bits long and requires an ACKNOWLEDGE signal after each byte. The devices have Master and Slave configurations. The Master device initiates and ends data transfer on the BUS and generates the clock signals in order to permit transfer. The EEPROM in a slave configuration is controlled by a unique address. Devices transmitting data are referred to as the Transmitter. The devices receiving the data are called Receiver.
START Condition (Recognition of the START bit) All commands are proceeded by the start condition, which is a High to Low transition of SDA when SCL is High. The device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. (See Fig.1-(b) START/STOP Bit Timing) STOP Condition (Recognition of STOP bit) All communications must be terminated by a stop condition, which is a Low to High transition of SDA when SCL is High. (See Fig.1-(b) START/STOP Bit Timing) Write Protect By Soft Ware Set Write Protect command and permanent set Write Protect command set data of 00h7Fh in 256 words write protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Acknowledge Acknowledge is a software used to indicate successful data transfers. The Transmitter device will release the BUS after transmitting eight bits. When inputting the slave address during write or read operation, the Transmitter is the -COM. When outputting the data during read operation, the Transmitter is the EEPROM. During the ninth clock cycle the Receiver will pull the SDA line Low to verify that the eight bits of data have been received. (When inputting the slave address during write or read operation, EEPROM is the receiver. When outputting the data during read operation the receiver is the -COM.) The device will respond with an Acknowledge after recognition of a START condition and its slave address (8bit). In WRITE mode, the device will respond with an Acknowledge after the receipt of each subsequent 8-bit word (word address and write data). In READ mode, the device will transmit eight bits of data, release the SDA line, and monitor the line for an Acknowledge. If an Acknowledge is detected and no STOP condition is generated by the Master, the device will continue to transmit the data. If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to standby mode. Device Addressing Following a START condition, the Master outputs the Slave address to be accessed. The most significant four bits of the slave address are the "device type indentifier." For this EEPROM it is "1010. " (For WP register access this code is "0110".) The next three bits identify the specified device on the BUS (device address). The device address is defined by the state of the A0,A1 and A2 input pins. This IC works only when the device address input from the SDA pin corresponds to the status of the A0,A1 and A2 input pins. Using this address scheme allows up to eight devices to be connected to the BUS. The last bit of the stream (R/W...READ/WRITE) determines the operation to be performed. R/W=0 R/W=1 Slave Address Set Pin A2 A2 GND GND A1 A1 GND Vcc A0 A0 VHV VHV WRITE (including word address input of Random Read) READ Device Address A2 A2 0 0 A1 A1 0 1 A0 A0 1 1 Read Write Mode R/W R/W R/W R/W Access Area 2kbit Access to Memory Access to Permanent Set Write Protect Memory Access to Set Write Protect Memroy Access to Clear Write Protect MEmory
Device Type 1010 0110
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
7/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
WRITE PROTECT PIN(WP) When WP pin set to Vcc (H level), write protect is set for 256 words (all address). When WP pin set to GND (L level), it is enable to write 256 words (all address). If permanent protection is done by Write Protect command, lower half area (007Fh address) is inhibited writing regardless of WP pin state. WP pin has a Pull-Down resistor. Please be left unconnected or connect to GND when WP feature is not in use. Confirm Write Protect Resistor by ACK According to state of Write Protect Resistor, ACK is as follows. State of Write WP Input Input Command ACK Protect Registor PSWP, SWP, CWP No ACK In case, Page or Byte Write protect by PSWP ACK (007Fh) SWP No ACK CWP ACK 0 PSWP ACK Page or Byte Write ACK In case, (007Fh) protect by SWP SWP No ACK CSP ACK 1 PSWP ACK Page or Byte Write ACK PSWP, SWP, CWP ACK 0 Page or Byte Write ACK In case, Not protect PSWP, SWP, CWP ACK 1 Page or Byte Write ACK
*- is Don't Care
Address WA7WA0 WA7WA0 WA7WA0 WA7WA0 WA7WA0 Address -
ACK No ACK ACK No ACK ACK ACK ACK
Data
Write Cycle(tWR) No ACK No ACK No No Yes Yes No No No No No Yes Yes No No ACK No ACK No ACK No ACK No ACK No ACK
D7D0 No ACK No ACK ACK ACK
D7D0 No ACK
No ACK No ACK ACK No ACK ACK No ACK ACK D7D0 No ACK ACK ACK ACK D7D0 ACK ACK No ACK ACK D7D0 No ACK ACK No ACK No ACK No ACK No ACK No ACK Data -
State of Write Protect Registor In case, protect by PSWP In case, protect by SWP In case, Not protect
Command PSWP, SWP, CWP SWP CWP PSWP PSWP, SWP, CWP
ACK No ACK No ACK ACK ACK ACK
Write Cycle During WRITE CYCLE operation data is written in the EEPROM. The Byte Write Cycle is used to write only one byte. In the case of writing continuous data consisting of more than one byte, Page Write is used. The maximum bytes that can be written at one time is 16 bytes.
S T A R T SDA LINE
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
W R I T E WA 7 RA /C WK
WORD ADDRESS WA 0 A C K D7
DATA
S T O P D0 A C K
Fig.33 Byte Write Cycle Timing
S T A R T SDA L IN E W R I T E WA 7 RA /C WK
S LA V E ADDRESS 1 0 1 0 A 2A 1A 0
W ORD A D D R E S S (n ) WA 0 A C K D7
D A TA (n) D0 A C K
D A TA (n + 1 5) D0 A C K
S T O P
Fig.34 Page Write Cycle Timing
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
8/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
With this command the data is programmed into the indicated word address. When the Master generates a STOP condition, the device begins the internal write cycle to the nonvolatile memory array. Once programming is started no commands are accepted for tWR (5ms max.). This device is capable of sixteen-byte Page Write operations. If the Master transmits more than sixteen words prior to generating the STOP condition, the address counter will "roll over" and the previously transmitted data will be overwritten. When two or more byte of data are input, the four low order address bits are internally incremented by one after the receipt of each word, while the four higher order bits of the address (WA7WA4) remain constant. Read Cycle During Read Cycle operation data is read from the EEPROM. The Read Cycle is composed of Random Read Cycle and Current Read Cycle. The Random Read Cycle reads the data in the indicated address. The Current Read Cycle reads the data in the internally indicated address and verifies the data immediately after the Write Operation. The Sequential Read operation can be performed with both Current Read and Random Read. With the Sequential Read Cycle it is possible to continuously read the next data. It is necessary to input "High" at last ACK timing.
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0 A C K RA /C WK R E A D D7 S T O P D0 A C K
S T A R T SDA L IN E
SLAVE ADDRESS 1 0 1 0 A 2 A 1A 0
W R I T E WA 7 RA /C WK
W ORD A D D R E S S (n ) WA 0
S T A R T
D A TA (n)
Fig.35 Random Read Cycle Timing
S T A R T SDA LINE R E A D D7 RA /C WK S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A2 A1 A0
DATA
It is necessary to input "High" at last ACK timing.
Fig.36 Current Read Cycle Timing Random Read operation allows the Master to access any memory location indicated by word address. In cases where the previous operation is Random or Current Read (which includes Sequential Read), the internal address counter is increased by one from the last accessed address (n). Thus Current Read outputs the data of the next word address (n+1). If an Acknowledge is detected and no STOP condition is generated by the Master (-COM), the device will continue to transmit data. (It can transmit all data (2kbit 256word)) If an Acknowledge is not detected, the device will terminate further data transmissions and await a STOP condition before returning to standby mode. If an Acknowledge is detected with the "Low" level (not "High" level), the command will become Sequential Read, and the next data will be transmitted. Therefore, the Read command is not terminated. In order to terminate Read input Acknowledge with "High" always, then input a STOP condition.
S T A R T SDA L IN E R E A D S T O P D0 A C K
SLAVE ADDRESS 1 0 1 0 A 2A 1A 0
D A T A (n ) D7 D0 A C K A C K D7
D A T A (n + x)
It is necessary to input "High" at last ACK timing.
RA /C WK
Fig.37
Sequential Read Cycle Timing With Current Read
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
9/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Write Protect Cycle
S T A R T SDA L IN E W R I T E * RA /C WK S T O P * A C K
*:D O N 'T C A R E
Technical Note
SLAVE ADDRESS 0 1 1 0 A 2A 1A 0
W ORD ADDRESS * A C K *
D ATA
WP
Fig. 38 Permanent Write Protect Cycle
Permanent set Write Protect command set data of 00h7Fh in 256 words write protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Permanent Set Write Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR, input command is canceled. Refer to P8/19 about reply of ACK in each protect state.
S T A R T SDA L IN E W R I T E * RA /C WK
SLAVE ADDRESS 0110001
W ORD ADDRESS * A C K *
D ATA * A C K
S T O P
WP
Fig. 39 Set Write Protect Cycle
*:D O N 'T C A R E
Permanent set Write Protect command set data of 00h7Fh in 256 words write protection block. Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Permanent Set Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR, input command is canceled. Refer to P8/19 about reply of ACk in each protect state.
S T A R T SDA L IN E W R I T E * RA /C WK S T O P * A C K
*:D O N 'T C A R E
SLAVE ADDRESS 0110011
W ORD ADDRESS * A C K *
D ATA
WP
Fig. 40 Clear Write Protect Cycle Clear Write Protect command can cancel write protection block which is set by set write Protect command. Cancel of write protection block which is set by permanent set Write Protect command at once is impossibility. When these commands are carried out, WP pin must be OPEN or GND. Permanent Clear Write Protect command needs tWR from stop condition same as Byete Write and Page Write, During tWR, input command is canceled. Refer to P8/19 about reply of ACk in each protect state.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
10/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
Software Reset Execute software reset in the event that the device is in an unexpected state after power up and/or the command input needs to be reset. Below are three types(Fig.39 -(a), (b), (c)) of software reset: During dummy clock, release the SDA BUS (tied to VCC by a pull-up resistor). During this time the device may pull the SDA line Low for Acknowledge or the outputting of read data.If the Master sets the SDA line to High, it will conflict with the device output Low, which can cause current overload and result in instantaneous power down, which may damage the device.
DUMMY CLOCKx14
STARTx2
SCL SDA
1
2
13
14
COMMAND COMMAND
Fig.39-(a) DUMMY CLOCKx14 + START+START
START DUMMY CLOCKx9 START
SCL SDA
1
2
8
9
COMMAND COMMAND
Fig.39-(b) START + DUMMY CLOCKx9 + START
STARTx9
SCL SDA
1
2
3
7
8
9
COMMAND COMMAND
Fig.39-(c) STARTx9
* COMMAND starts with start condition.
Acknowledge polling Since the IC ignores all input commands during the internal write cycle, no ACK signal will be returned. When the Master sends the next command after the Write command, if the device returns an ACK signal it means that the program is completed. No ACK signal indicates that the device is still busy. Using Acknowledge polling decreases the waiting time by tWR=5ms. When operating Write or Current Read after Write, first transmit the Slave address (R/W is"High" or "Low"). After the device returns the ACK signal continue word address input or data output.
During the internal write cycle, no ACK will be returned. (ACK=High)
S T A R T S T O P S T A R T
THE FIRST WRITE COMMAND
WRITE COMMAND
SLAVE ADDRESS
A C K H
S T A R T
SLAVE ADDRESS
A C K H
tWR THE SECOND WRITE COMMAND
S T A R T
SLAVE ADDRESS
A C K H
S T A R T
SLAVE ADDRESS
A C K L
WORD ADDRESS
A C K L
DATA
A C K L
S T O P
tWR
After the internal write cycle is completed, ACK will be returned (ACK=Low). Then input next Word Address and data.
Fig.40 Successive Write Operation By Acknowledge Polling
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
11/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
WP effective timing WP is normally fixed at "H" or "L". However, in case WP needs to be controlled in order to cancel the Write command, pay attention to "WP effective timing" as follows: The Write command is canceled by setting WP to "H" within the WP cancellation effective period. The period from the START condition to the rising edge of the clock (which takes in the data DO - the first byte of the Page Write data) is the `invalid cancellation period'. WP input is considered inconsequential during this period. The setup time for the rising edge of the SCL, which takes in DO, must be more than 100ns. The period from the rising edge of SCL (which takes in the data D0) to the end of internal write cycle (tWR) is the `effective cancellation period'. When WP is set to "H" during tWR, Write operation is stopped, making it necessary to rewrite the data. It is not necessary to wait for tWR (5ms max.) after stopping the Write command by WP because the device is in standby mode.
The
rising edge of the clock which take in D0
SCL SDA
D0
SCL SDA
D1 D0
The rising edge of SDA
ACK AN ENLARGEMENT
ACK
AN ENLARGEMENT
S A T SLA VE C WORD A K R ADDRESS L ADDRESS T A A C C K D7 D6 D5 D4 D3 D2 D1 D0 K L L
SDA
DATA
A C K L
S T O P
tWR
WP cancellation
WP cancellation effective period
Stop of the write operation Data is not
WP
invalid period
No data will be written
guaranteed
Fig.41 WP effective timing Command cancellation from the START and STOP conditions Command input is canceled by successive inputs of START and STOP conditions. (Refer to Fig.42) However, during ACK or data output, the device may set the SDA line to Low, making operation of the START and STOP conditions impossible, and thus preventing reset. In this case execute reset by software. (Refer to Fig.39) The internal address counter will not be determined when operating the Cancel command by the START and STOP conditions during Random, Sequential or Current Read. Operate a Random Read in this case.
SCL
SDA
1
0
1
0
START CONDITION STOP CONDITION
Fig.42 Command cancellation by the START and STOP conditions during input of the Slave Address
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
12/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
I/O Circuit SDA Pin Pull-up Resistor A pull-up resistor is required because SDA is an NMOS open drain. Determine the resistor value of (RPU) by considering the VIL and IL, and VOL-IOL characteristics. If a large RPU is chosen, the clock frequency needs to be slow. A smaller RPU will result in a larger operating current. Maximum RPU The maximum of RPU can be determined by the following factors. The SDA rise time determined by RPU and the capacitance of the BUS line(CBUS) must be less than tR. In addition, all other timings must be kept within the AC specifications. A When the SDA BUS is High, the voltage at the SDA BUS is determined from the total input leakage(IL) of all devices connected to the BUS. RPU must be higher than the input High level of the microcontroller and the device, including a noise margin 0.2VCC. VCC-ILRPU-0.2 VCC VIH
RPU 0.8VCC-VIH IL
IL Microcontroller RPU A SDA PIN BR34E02
Examples: When VCC =3V, IL=10A, VIH=0.7 VCC According to RPU

IL
0.8x3-0.7x3 10x10 300 [k] Fig.43 I/O Circuit
-6
THE CAPACITANCE OF BUS LINE (CBUS)COMPUTER
Minimum RPU The minimum value of RPU is determined by following factors. Meets the condition that VOLMAX=0.4V, IOLMAX=3mA when the output is Low. VCC-VOL IOL RPU VCC-VOL IOL VOLMAX=0.4V must be lower than the input Low level of the microcontroller and the EEPROMincluding the recommended noise margin of 0.1VCC. VOLMAX VIL-0.1 VCC Examples: VCC=3V, VOL=0.4V, IOL=3mA, the VIL of the controller and the EEPROM is VIL=0.3VCC, According to RPU
RPU 3-0.4 3x10 -3
867 VOL=0.4V VIL=0.3x3 =0.9V o that condition is met
and and
SCL Pin Pull-up Resistor When SCL is controlled by the CMOS output the pull-up resistor at SCL is not required. However, should SCL be set to Hi-Z, connection of a pull-up resistor between SCL and VCC is recommended. Several k are recommended for the pull-up resistor in order to drive the output port of the microcontroller. A0, A1, A2, WP Pin connections Device Address Pin (A0, A1, A2) connections The status of the device address pins is compared with the device address sent by the Master. One of the devices that is connected to the identical BUS is selected. Pull up or down these pins or connect them to VCC or GND. Pins that are not used as device address (N.C.Pins) may be High, Low, or Hi-Z. WP Pin connection The WP input allows or prohibits write operations. When WP is High, only Read is available and Write to all address is prohibited. Both Read and Write are available when WP is Low. In the event that the device is used as a ROM, it is recommended that the WP input be pulled up or connected to VCC. When both READ and WRITE are operated, the WP input must be pulled down or connected to GND or controlled.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
13/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
Microcontroller connection Concerning Rs 2 The open drain interface is recommended for the SDA port in the I C BUS. However, if the Tri-state CMOS interface is applied to SDA, insert a series resistor (Rs) between the SDA pin of the device and the pull up resistor RPU is recommended, since it will serve to limit the current between the PMOS of the microcontroller, and the NMOS of the EEPROM. Rs also protects the SDA pin from surges. Therefore, Rs is able to be used though open drain inout of the SDA port.
ACK
RPU
SCL
RS
SDA
'H'OUTPUT OF CONTROLLER "L" OUTPUT OF EEPROM
CONTROLLER
EEPROM
The "H" output of controller and the "L" output of EEPROM may cause current overload to SDA line.
Fig.44 I/O Circuit
Fig.45 Input/Output Collision Timing Rs Maximum The maximum value of Rs is determined by following factors. SDA rise time determined by RPU and the capacitance value of the BUS line (CBUS) of SDA must be less than tR. In addition, the other timings must be within the timing conditions of the AC. A When the output from SDA is Low, the voltage of the BUS at is determined by RPU, and Rs must be lower than the input Low level of the microcontroller, including recommended noise margin (0.1VCC).
VCC RPU A RS IOL
BUS CAPACITANCE
(VCC-VOL)xRS RPU+RS
VOL
+
VOL+0.1VCC VIL
RS
VIL-VOL-0.1VCC 1.1VCC-VIL
x
RPU
Examples : When VCC=3VVIL=0.3VCC VOL=0.4VRPU=20k
EEPROM
VIL
CONTROLLER
According to RS
0.3x3-0.4-0.1x3 1.1x3-0.3x3
x
20x103
Fig.46 I/O Circuit 1.67k
Rs Minimum The minimum value of Rs is determined by the current overload during BUS conflict. Current overload may cause noises in the power line and instantaneous power down. The following conditions must be met, where "I" is the maximum permissible current, which depends on the Vcc line impedance as well as other factors. "I" current must be less than 10mA for EEPROM.
Vcc RS
RPU
I Vcc I
RS
MAXIMUM CURRENT
"L" OUTPUT
RS
Examples: When VCC=3V, I=10mA RS 3 10x10-3
"H" OUTPUT
CONTROLLER
EEPROM
300
Fig.47 I/O Circuit
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
14/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
I2C BUS Input / Output equivalent circuits Input (A0,A2,SCL)
Technical Note
Fig.48 Input Pin Circuit
Input / Output (SDA)
Fig.49 Input / Output Pin Circuit
Input (A1)
Fig.50 Input Pin Circuit
Input (WP)
Fig.51 Input Pin Circuit
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
15/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
Power Supply Notes VCC increases through the low voltage region where the internal circuit of IC and the microcontroller are unstable. In order to prevent malfunction, the IC has P.O.R and LVCC functionality. During power up, ensure that the following conditions are met to guaranty P.O.R. and LVCC operability.
1. "SDA='H'" and "SCL='L' or 'H'". 2. Follow the recommended conditions of tR, tOFF, Vbot so that P.O.R. will be activated during power up.
VCC tR
Recommended conditions of tR, tOFF, Vbot tR
tOFF 0 Vbot
tOFF Above 10ms Above 10ms
Vbot Below 0.3V Below 0.2V
Below 10ms Below 100ms
Fig.52 VCC rising wavefrom
3. Prevent SDA and SCL from being "Hi-Z". In case that condition 1. and/or 2. cannot be met, take following actions. A) If unable to keep Condition 1 (SDA is "Low" during power up) Make sure that SDA and SCL are "High" as in the figure below.
VCC SCL
tLOW
SDA After Vcc becomes stable tDH tSU:DAT After Vcc becomes stable tSU:DAT
Fig.53 SCL="H" and SDA="L"
Fig.54 SCL="L" and SDA="L"
B) If unable to keep Condition 2 After the power stabilizes, execute software reset. (See page 9,10) C) If unable to keep either Condition 1 or 2 Follow Instruction A first, then B
LVCC Circuit The LVCC circuit prevents Write operation at low voltage and prevents inadvertent writing. A voltage below the LVCC voltage (1.2V typ.) prohibits Write operation. VCC Noise Bypass Capacitor Noise and surges on the power line may cause abnormal function. It is recommended that bypass capacitors (0.1F) be attached between VCC and GND externally.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
16/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Technical Note
Notes for Use 1) Descrived numeric values and data are design representative values, and the values are not guaranteed.
2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI. 3) Absolute maximum ratings If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded, LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that conditions exceeding the absolute maximum ratings should not be impressed to LSI. 4) GND electric potential Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of GND terminal. 5) Heat design In consideration of permissible dissipation in actual use condition, carry out heat design with sufficient margin. 6) Terminal to terminal short circuit and wrong packaging When to package LSI on to a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may destruct LSI. And in the case of short circuit between LSI terminals and terminals and power source, terminal and GND owing to foreign matter, LSI may be destructed. 7) Use in a strong electromagnetic field may cause malfunction, therfore, evaluate design sufficiently.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
17/18
2009.04 - Rev.A
BR34E02FVT-W, BR34E02NUX-W
Ordering part number
Technical Note
B
R
3
BUS type 34I2C
4
E
0
02= 2K
2
F
Packagr
V
T
-
W
E
2
ROHM type
Priduct type Capacity
W : Double cell Packaging and forming specification E2: Embossed tape and reel (TSSOP-B8) TR: Embossed tape and reel (VSON008X2030)
FVT:TSSOP-B8 NUX:VSON008X2030
SSOP-B8

3.0 0.2 (MAX 3.35 include BURR)
876 5
Tape Quantity
0.3MIN
Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
6.40.3
4.40.2
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
1234
1.150.1
0.15 0.1 S 0.1 +0.06 0.22 -0.04 0.08
M
0.1
(0.52)
0.65
1pin
(Unit : mm)
Direction of feed
Reel
Order quantity needs to be multiple of the minimum quantity.
VSON008X2030
2.00.1
3.00.1

Tape Quantity
S
+0.03 0.02 -0.02 (0.22)
Embossed carrier tape 4000pcs TR
The direction is the 1pin of product is at the upper right when you hold
1PIN MARK
1.0MAX
Direction of feed
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S
1.50.1 0.5
C0.25
0.30.1
8
5
0.25
1.40.1
1
4
+0.05 0.25 -0.04
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
18/18
2009.04 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM Co.,Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
www.rohm.com (c) 2009 ROHM Co., Ltd. All rights reserved.
R0039A

▲Up To Search▲

Price & Availability of BR34E02FVT-W

	To Download BR34E02FVT-W Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .